Apple

The technology behind Apple’s M1 UltraFusion chip interconnect

The technology behind Apple's M1 UltraFusion chip interconnect

Building high-performance microprocessors is becoming increasingly tricky and expensive these days, which is why developers must opt ​​for sophisticated packaging technologies with designs aimed at performance-intensive applications. Apple admits that to make its M1 Ultra processor it had to merge two M1 Max system-on-chips, but what it didn’t say is that it had to use one of the most advanced packaging technologies. advances from TSMC to build the M1 Ultra.

Fortunately, unofficial sources are less secretive than Apple and were able to dig up additional details about Apple’s UltraFusion interprocessor interconnect which offers 2.5TB/s bandwidth. DigiTimes reports that Apple’s M1 Ultra processor* used TSMC’s chip-on-wafer-on-substrate with silicon interposer (CoWoS-S)-based 2.5D packaging process to build the M1 Ultra. Similar technologies are used by companies like AMD, Nvidia, and Fujitsu to build their high-performance processors for data centers and high-performance computing (HPC).

Apple’s M1 Ultra is certainly a terrific design. Each M1 Max SoC features a die size of 432 mm2, so the interposer used by the M1 Ultra must be larger than 860 mm2. It’s quite massive but not unheard of. AMD and Nvidia use even larger interposers with their compute GPUs with high-bandwidth memory.

* – We don’t know exactly what to call the M1 Ultra. Technically, it’s a system-on-a-chip in a package, or SoCiP, but that can be a bit long, so we’ll just call it a “processor” for now.

(Image credit: Apple)

But TSMC’s CoWoS-S isn’t the only option the world’s largest semiconductor maker has for bandwidth-intensive applications. Some experts have speculated that Apple may opt for TSMC’s InFO_LSI technology for integrating ultra-high bandwidth chips. Unlike CoWoS-S, InFO_LSI uses localized silicon interconnects instead of large and expensive interposers. Intel’s Integrated Chip Interconnect Bridge (EMIB) uses the same concept.

Bearing in mind that Apple demonstrated an M1 Max die shot with a massive I/O block that looks like a local interconnect designed to connect to an intermediate chip, it’s no surprise many people thought that Apple was using InFO_LSI.

(Image credit: TSMC)

But there’s a reason Apple may have stuck with the potentially more expensive CoWoS-S. TSMC’s InFO_LSI was officially introduced in August 2020 and was expected to complete qualification in Q1 2021. Meanwhile, Apple’s M1 Max was expected to enter volume production in Q2 or Q3 2021, so Maybe Apple just didn’t have enough time to implement InFO_LSI. That or he decided not to take a risk and stick with a technology that is well known and widely used by various companies.

(Image credit: Apple)

Another element that DigiTimes discloses is that Unimicron Technology is now the sole supplier of ABF (Ajinomoto build-up film) substrates to Apple, as it is the only company capable of supplying the quality and quantity that Apple needs. Anyway, while we now know what packaging technology Apple used to enable its UltraFusion interconnect, we still have no idea about its clocks, bus width, power, etc., so stay tuned.